Circuit Designs Programmable Divider

发布于:2021-10-25 11:20:46

Mobile Wi-Max Radio Phase Locked Loop Design
Eldon Staggs Technical Director

PLL Design Agenda
Introduction to Mobile Wi-Max Phase Locked Loop Architecture
System level requirements Architecture tradeoffs

Circuit Designs
Programmable Divider Phase/Frequency Detector Charge Pump Reference Oscillator Voltage Controlled Oscillator

PLL Design Convergence
System / Circuit simulation results Conclusion

IC Convergence
3D EM Accuracy Speed, Capacity & Reliability in solving large circuits Solve in Time & Frequency Use established design flows.

Ansoft Designer

Nexxim

Q3D Extractor

HFSS

Cadence ADE & Virtuoso Layout

Mobile Wi-Max (IEEE802.16e)
WiMax (IEEE802.16)
Delivery of last mile wireless broadband access Fixed, Portable and Mobile options 40Mbps capacity up to 10km per channel OFDM with QPSK/QAM16/QAM64

Mobile WiMax (IEEE802.16e)
15Mbps capacity up to 3km per channel, 2.3-2.7GHz No Line-of-Sight required

Transceiver Block Diagram
PLL Design

Phase Locked Loop Architecture

PLL Architecture
System Level Requirements
(WiMAX) IEEE 802.16 – Fixed and Mobile Broadband Wireless Access Systems.
IEEE 802.16e is an amendment, which includes mobile stations.

Several Frequency Bands
2.3-2.7GHz, 3.4-4.99GHz, 5.15-5.85GHz, and 10-66GHz. Fractional-N Phase Locked Loop designed for the 2.3-2.7GHz band. 125kHz Resolution

Fabrication Process
UMC 0.13μm process chosen for this design

Settling Time
Taken from Sierra Monolithics PLL data sheet (50μs) Specification is not clear

PLL Architecture
PLL Architecture Tradeoffs
Integer N PLL
125kHz Reference pushes N from 18400 to 21600 (2700/.125) Loop Filter cutoff (<12.5kHz) produces long settling time VCO Phase Noise increased by 20*log10(N) ≈ 85dB
Ref

Freq(t)

PFCOMP
VCO

AMP

VCO
t

N

Multi-Modulus Fractional PLL
Fractional value between N and 2N-1 (64-127) Sigma Delta Modulator (Programmable resolution) Large Reference (20MHz) for good tradeoff with settling time Reduced N impact on phase noise by 45dB over Integer N

Multi-Modulus PLL Architecture
Voltage Controlled Oscillator Upconverter , FVCO = (2/3)FRF Programmable Divider Sigma Delta Modulator
20MHz 2.5mA

Reference Oscillator Phase/Frequency Detector Charge Pump Loop Filter
1533-1800MHz

OSC

PFD

CP
64-127

VCO Fout(I)

Div-N ΣΔ

Div-2

2300-2700MHz

Fout(Q)

Design Goals
PARAMETER
VCO Frequency Fout (I and Q) Lock-Time Phase Noise @ 10kHz Phase Noise @ 100kHz Phase Noise @ 1MHz Reference Tuning Range Charge Pump Current Divider -95 dBc/Hz -95 dBc/Hz -120 dBc/Hz 20MHz 0.15 V 2.5mA 64 127 1.05 V 25uA Trickle 2/3 Cascaded Design

LOW GOAL
1.533 GHz 2.3 GHz

HIGH GOAL
1.8 GHz 2.7 GHz 50μs -90 dBc/Hz -90 dBc/Hz -115 dBc/Hz

NOTES
Fout / 1.5 125 kHz Resolution 3rd Order Loop Filter ~ 1deg. RMS ~ 1deg. RMS ~ 1deg. RMS

System Simulations
?

Behavioral System Simulations
?

High level Synthesizer libraries
? ?

Lock Time estimation Phase Noise performance Detailed Multi-Modulus Divider Spurious performance Verify system detail needed for Circuit level

?

Lower level Abstraction
? ? ?

?

System / Circuit Co-Simulation
? ? ?

Replace system components with Circuits for verification Noise information entered into higher level models Future inclusion of layout extracted EM designs

High Level Behavioral System
Ideal Divider fed by Sigma Delta Modulator Loop Filter
Ref Up UP

Fref = 20MHz

RDMUX
REAL

SP SINK

Vtune Freq_Lock
Freq(t) t

Fout
Tune VCO/N

PFDET
VCO

CPUMP
DOWN

Dow n

1500 0.2nF 76nF 3nF

VCODIVBYN
dN

VCO

CDMUX

SINK

PN

L(fm) fm

Fout / (N+deltaN)
0 100 0

PNP

CSCALE

Sx x ( f ) Fout_PSD

deltaN
0 U9 System7

Fout / (N+deltaN)

CLK_in

sdm_out

-D

Z

Detailed Behavioral System
Multi-Modulus Prescalar Divider Modeled
FS2 = FS / K2
RATE CHANGER
Freq(t) t

VCO

CDMUX

Fref = 20MHz
Ref Up UP

CSCALE

Sx x( f )

Sine_out

PFDET
VCO

CPUMP
DOWN

Tune

V C O/N

Down

1500 0.2nF 76nF 3nF

VCODIVBYN
dN

V CO

PN

0 U10 Sqr2Sin 100

0

0

Fout Sqr_in

PRESCALAR (64-127)

Fin

-D

Z

P0

P1

P2

P3

P4

P5

P0

P1

P2

P3

P4

P5

U9 SigmaDelta

U1 bit_cntrl

Multi-Modulus Divider

SDM_in CLK_in sdm_out

Prescalar Bit Controller

Phase Locked Loop Circuit Designs
20MHz 2.5mA 1533-1800MHz

OSC

PFD

CP
64-127

VCO Fout(I)

Div-N ΣΔ

Div-2

2300-2700MHz

Fout(Q)

Reference Oscillator
20MHz 2.5mA 1533-1800MHz

OSC

PFD

CP
64-127

VCO Fout(I)

Div-N ΣΔ

Div-2

2300-2700MHz

Fout(Q)

Reference Oscillator
Design Specifications
External Crystal Resonator Reference Frequency = 20MHz CMOS output levels

Cs
5.5e-015

Rs
50

Ls
0.011585

Equivalent Circuit
Ls = 11.585mH, Rs = 50Ω Cs = 5.5fF, Cp = 2pF

Cp
2p

Crystal Resonant Frequency
1 = 19.966 MHz 2π LS ? CEQ Cp ? Cs = 5.485e ? 15 CEQ = Cp + Cs FXTAL =

Pierce Oscillator
Circuit Schematic
External Crystal and Oscillator Excellent frequency stability Low Voltage/Low Current

Inverter

Pierce Oscillator
Simulation Results
Oscillation Frequency = 20.001MHz

Time Domain Output Output Phase Noise

Phase/Frequency Detector & Charge Pump
20MHz 2.5mA 1533-1800MHz

OSC

PFD

CP
64-127

VCO Fout(I)

Div-N ΣΔ

Div-2

2300-2700MHz

Fout(Q)

Phase/Frequency Detector
Design Specifications
Reference Input/Comparison Frequency: 20MHz Reference & Divided VCO signal levels: CMOS rails (0/1.2V) UP/DN control output signal levels: CMOS rails (0/1.2V) Edge-triggered; non-duty-cycle-dependent

Iup fref fdiv

Itr Icp

PFD
Idn

Zlpf

Phase/Frequency Detector
General Operation
Provide control signals to Charge Pump based on edgedetected Phase/Frequency Δ between VCO & REF signals.
VCO lags REF: VCO leads REF: VCO = REF: Pulse UP pin; bring DN pin LOW. (Pump-UP) Pulse DN pin; bring UP pin HIGH. (Pump-DOWN) Bring DN pin LOW, UP pin HIGH (retain charge)

Phase/Frequency Detector
Circuit Schematic

Condition: 1) VCO Lags REF (VCO/N<20MHz): Pump UP 2) VCO Leads REF (VCO/N>20MHz): Pump DN 3) VCO = REF: Locked

Charge Pump
Design Specifications
Programmable KΦ (625uA/2.5mA per 2π radians) for ‘fastlock’ option. Programmable Trickle current (25?A/250?A) UP/DN control input signal levels: CMOS rails (0/1.2V)
fref fdiv Iup Itr Icp Zlpf

PFD
Idn

General Operation

Source/Sink/Retain Loop Filter charge based on control signals from Phase/Frequency Detector. VCO lags REF: Add charge to Loop Filter (Pump-UP) VCO leads REF: Remove charge from Loop Filter (Pump-DOWN) VCO = REF: Retain charge (neither add nor remove)

Charge Pump
Circuit Schematic
Programmable Charge Pump
Kφ = 2.5mA/2π or 625μA/2π, for Vφ = Vdd or 0

Programmable Trickle Current
Itrickle = 250μA or 25μA, for Vtrickle = Vdd or 0 Pull-UP Current Source

Trickle Current Circuitry

Pull-DOWN Current Sink

UP/DOWN Switches

Phase/Frequency Detector, Charge Pump, and Loop Filter
Test Bench Schematic
Programmable Charge Pump & Loop Filter 1) Vmode=Vdd: Kphi=2.5mA/2π, LoopFilter=FastLock 2) Vmode=0: Kphi=625μA/2π, LoopFilter=LowNoise 3) Vtrickle=Vdd: I_trickle=250μA 4) Vtrickle=0: I_trickle=25μA

Phase/Frequency Detector & CP Nexxim Transient Simulation Results for: VCO lagging REF (pump-up) by 5%

Phase/Frequency Detector & CP Nexxim Transient Simulation Results for: VCO leading REF (pump-down) by 5%

Loop Filter
20MHz 2.5mA 1533-1800MHz

OSC

PFD

CP
64-127

VCO Fout(I)

Div-N ΣΔ

Div-2

2300-2700MHz

Fout(Q)

Loop Filter
We chose a standard 3rd-order topology. Equations were taken from Deans Book
“PLL Performance, Simulation, and Design”, 3rd Edition, Dean Banerjee

Loop bandwidth designed to 75kHz. Other required parameters:
Kphi = 2.5mA Kvco = 150MHz/V Phase Margin = 60deg N = 80 Gamma = 1.025 T3/T1 Ratio = 0.6 Lock-time < 50μs
1500 0.2nF 0 100 0 76nF 3nF 0

Loop Filter Response
Phase Margin
At 0dB Crossing, Margin is about 60 degrees
3rd Order Loop Gain
100 50 0 [dB] -50 -100 -150 -200 360

Gain Phase

270 180 90 0 -90 -180 -270 -360

1

10

100

1000

10000

100000

Frequency (kHz)

[deg]

Voltage Controlled Oscillator
20MHz 2.5mA 1533-1800MHz

OSC

PFD

CP
64-127

VCO Fout(I)

Div-N ΣΔ

Div-2

2300-2700MHz

Fout(Q)

Voltage Controlled Oscillator
Design Specifications
Voltage gain (150MHz/V) Tuning range
Output Frequency: 1.533GHz – 1.8GHz Input Voltage: 150mV – 1050mV, 2 bands (2*0.9*150=270MHz)

– Band1: 1540MHz at 200mV, 1660MHz at 1000mV – Band2: 1674MHz at 200mV, 1794MHz at 1000mV Two Differential CML outputs
64-127 Programmable Divider input 3/2 Upconverter input

Phase Noise
PLL output dominated by VCO Increased by 20*log10(3/2) to PLL output

Voltage Controlled Oscillator
Block Diagram
Negative Gm Oscillator Tank Circuit
Single Spiral Inductor Switched Capacitor Banks Switched Varactor Banks

FLO =

1 ≈ KVCO *VTUNE 2π L ? C (VTUNE )

Feedback Transistors
Negative tank resistance

Current Source
Stable input independent source

Buffers
CMOS-to-CML converters

Voltage Controlled Oscillator
Vhigh

Circuit Schematic
Negative Gm Oscillator Tank Capacitance
Switched Banks

p_12_rf

p_12_rf

Twin, Tripple Well RFCMOS

UMC 0.13um 1.2V/3.3V

0 corem os_corner=tt iom os_corner=tt cirspl_case=typ sqskspl_case=typ m cap_case=typ im varm is12_case=typ varm is33_case=typ vardio_case=typ npn_vn_case=typ npn_vs_case=typ pnp_vn_case=typ rnhr_case=typ rnnpo_case=typ rnppo_case=typ diodn_esd_case=ty p diop_esd_case=typ pad_rf_case=typ tune Vctl

V
Vhigh Vdd Vtune Vctl_0

lf=0.12u w f=1.8u nf=16 M=2 w t=28.8u l_cr20k_rf p_ls=5.9n do=150u w =4.5u s=1.5u nt=7.5

lf=0.12u w f=1.8u nf=16 M=2 w t=28.8u

0

V

Vhigh Vdd Pos

Vhigh

0

Neg Vctl_0

0

0

0 Vtune

LC Tank
n_12_rf 0

tune Vctl

1 FLO = 2π L ? C (VTUNE )
0

Vhigh

p_12_rf

p_12_rf 0

n_12_rf

lf=0.12u w f=3u nf=16 M=2 w t=48u

lf=0.12u w f=3u nf=16 M=2 w t=48u

0

lf=0.12u w f=1.8u nf=16 M=2 w t=28.8u

lf=0.12u w f=1.8u nf=16 M=2 w t=28.8u

A

5p

C124

n_12_rf

n_12_rf 0

0 n_12_rf

C125 0

0

lf=0.12u w f=1.5u nf=16 M=1 w t=24u

lf=0.12u w f=6u nf=16 M=4 w t=96u l=10u w=2u m=16 rnhr_rf r_zbt_m=0.304k

0

C78

Current Source

lf=0.12u w f=1.8u nf=16 M=4 w t=28.8u Vhigh 5p

0

5p

A

Voltage Controlled Oscillator
Varactor Switch Tank Capacitance
C=2Cfixed+Csw+Cvar(Vtune) Transmission gates
1.2V enables Capacitor 0V disables Capacitor
var_0 Vtune lf=0.12u wf=5.4u nf=16 M=4 wt=86.4u var_1 0 lf=0.12u wf=1.8u nf=16 M=4 wt=32u Vdd 0 Vdd Pos l=491n w=8u nf=6 m=3 l=491n w=8u nf=6 m=3 varmis_12_rf cox_m=755.9f var_0 varmis_12_rf cox_m=755.9f Neg Vh 0 var_1 0

C_var

varmis_12_rf cox_m=602.4f l=587n w=8u nf=6 m=2 0

varmis_12_rf cox_m=602.4f l=587n w=8u nf=6 m=2

Vl

lf=0.12u wf=5.4u nf=16 M=4 wt=86.4u

lf=0.12u wf=1.8u nf=16 M=4 wt=32u

0

mimcaps_rf c_tot_m=0.522p Vdd l=22u w=22u M=1 0

C_fixed
mimcaps_rf c_tot_m=1.034p

Inverters
Allow single bit control

p_12_rf Vctl_0 lf=0.12u wf=1.8u nf=16 M=4 wt=32u 0

p_12_rf mimcaps_rf c_tot_m=1.034p 0

Vdd

Vdd ctl_1

0

n_12_rf

lf=0.12u wf=1.8u nf=16 M=4 wt=32u

l=31.3u w=31.3u M=1

l=31.3u w=31.3u M=1 wt=28.8u M=1 nf=16 wf=1.8u lf=0.12u 0 Vdd

ctl_0 n_12_rf n_12_rf

ctl_0 mimcaps_rf c_tot_m=0.556p n_12_rf l=22.72u w=22.72u M=1

C_sw
mimcaps_rf c_tot_m=0.556p l=22.72u w=22.72u M=1

Switch Inverters

lf=0.12u wf=5.4u nf=16 M=4 wt=86.4u

0 Vdd

lf=0.12u wf=5.4u nf=16 M=4 wt=86.4u

0

Vdd

0

ctl_1

wt=28.8u M=1 nf=16 wf=1.8u lf=0.12u

0 Vdd

p_12_rf

p_12_rf

lf=0.12u wf=1.8u nf=16 M=4 wt=32u

0 Vh

lf=0.12u wf=1.8u nf=16 M=4 wt=32u

0 Vl

Varactor Switch - Vctl=0V enables var_0 - Vctl=1.2V enables var_1 Capacitor Switch - Vctl=0V enables ctl_0 - Vctl=1.2V enables ctl_1

n_12_rf

n_12_rf

lf=0.12u wf=5.4u nf=16 M=4 wt=86.4u

0

lf=0.12u wf=5.4u nf=16 M=4 wt=86.4u

0

Voltage Controlled Oscillator
Tuning Frequency
KVCO=150MHz/V from 200mV to 1V in each band Band1: 1540MHz to 1660MHz (0.2 to 1V) Band2: 1674MHz to 1794MHz (0.2 to 1V)

Voltage Controlled Oscillator
Spectral Response
Third Harmonic about -20dBc Phase Noise increase by 20*log10(3/2) to PLL output

Multi-Modulus Programmable Divider
20MHz 2.5mA 1533-1800MHz

OSC

PFD

CP
64-127

VCO Fout(I)

Div-N ΣΔ

Div-2

2300-2700MHz

Fout(Q)

Programmable Divider
Design Specifications Fvco = 2/3 Frf => 1.533GHz ≤ Fin ≤ 1.8GHz Fref = 20MHz => 76.667 ≤ Ndiv ≤ 90 6-bit Divider word from Sigma-Delta Modulator CMOS I/O levels for control inputs and PFD input CML differential levels from VCO input Noise outside loop bandwidth < -160dBc/Hz
Fout

PRESCALER PRESCALAR (64-127) (64-127)
P2 P3 P0 P1 P4 P5

Fin

P0

P1

P2

P3

P4

SDM_in CLK_in sdm_out

Prescalar Bit Controller

P5

U9 SigmaDelta

Programmable Divider
Block Diagram

Fin = Ndiv = 2n + 2n?1 ? pn?1 + 2n?2 ? pn?2 +Λ + 2 ? p1 + p0 Fout
Integer frequency division between 64 and 127 (N=6) Output edge compared with reference in PFD
Reference: C.S. Vaucher, et. al., “A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-um CMOS Technology”, IEEE J. SolidState Circuits, vol. 35, No. 7, 1039-1045, July 2000.

Programmable Divider
Top Level Circuit Schematic
5 FIN = 64 + ∑ Pn ? 2n , Pn = {0 | 1} FOUT n =0

Divide-by-2/3 Block

2/3 Cell

2/3 Cell

2/3 Cell

2/3 Cell

2/3 Cell

2/3 Cell

CML to CMOS Converter

CMOS to CML Converter

Programmable Divider
CML Divide-by-2/3 Circuit
D-Latch Buffered D-Latch

AND Gate

Programmable Divider
CML-to-CMOS Converter

Differential-to-Single Ended Buffer

Inverter Amplification To CMOS Levels

Programmable Divider
CMOS-to-CML Converter

CML Differential Pair Driven by CMOS Inverters

Programmable Divider
Divider Transient Simulation Results at Maximum and Minimum Divide Ratio Setting

Sigma-Delta Modulator
20MHz 2.5mA 1533-1800MHz

OSC

PFD

CP
64-127

VCO Fout(I)

Div-N ΣΔ

Div-2

2300-2700MHz

Fout(Q)

Sigma-Delta Modulator
Design Specifications
MASH 1-1-1 Architecture (3rd-order). 15-Bit Accumulators. Fractional Resolution = 20MHz/2^15 = 610Hz. The purpose of the circuit is to dither the divide ratio to achieve the desired fraction. The instantaneous divide ratio equals N+dN(t), where N is the base divide ratio and dN(t) can be an integer value between -3 to +4 at each cycle of the divided signal.

Sigma-Delta Modulator
Block Diagram
Fractional Input between 64 and 127 Dithered Output for spurious improvement Accumulators for Noise improvement
sdm_out

OV ERFLOW

RC ST ON

X

k

S

CLK

RT T OFX R CONST
S

OV ERFLOW

1- Z

-M

CLK

OVE RFLOW

1- Z
SINK

-M

1- Z

-M

S

CLK

CLK_in

Sigma-Delta Noise Spectrum
Noise Shaping
ΣΔ Modulators push noise to higher frequencies Loop Filter used to remove ΣΔ noise
“Principles of Sigma-Delta Modulation for Analog-to-Digital Converters”, Motorola Application Note by Sangil Park.

Phase Locked Loop Design Convergence

PLL Design Summary
Phase Locked Loop Architecture
Fractional-N PLL (2.3-2.7GHz) VCO (1.53-1.8GHz) output upconverted by (3/2) Fractional Divider between 64 and 127 ΣΔ Noise shaping/Spur suppression

20MHz

2.5mA

1533-1800MHz

OSC

PFD

CP
64-127

VCO Fout(I)

Div-N ΣΔ

Div-2

2300-2700MHz

Fout(Q)

PLL Frequency Response
Output Spectrum & Phase Noise Response

PLL Transient Response
Settling Time (~40μs) & Tune Frequency

PLL Design Summary
Circuit Designs
VCO and Reference Oscillator
Convergence of Time & Frequency domains Settling Times, Spectral Content and Phase Noise

PFD, CP and Loop Filter
Convergence of Time & Frequency domains Phase Detection/Margin, Loop Gain and Bandwidth

Programmable Divider and ΣΔ Modulator
Convergence of Analog (Circuit) & Digital (System) designs 15-bit digital ΣΔ Modulator modeled in behavioral system 6-stage Programmable Divider modeled in circuit

PLL IC Design Flow
Design Flow
System Design and Behavioral Modeling

Design Tools
Ansoft Designer Matlab HDL Spreadsheet Cadence Virtuoso Schematic Ansoft Nexxim Cadence Spectre Cadence Ultra-sim Cadence Virtuoso-XL Cadence Encounter P&R Ansoft HFSS Ansoft Q3D Ansoft TPA Cadence Assura DRC/LVS Mentor Calibre DRC/LVS

Schematic Entry and Design Environment

Time and Frequency Domain Circuit Simulation

Layout

Electromagnetic Extraction

Parasitic Extraction, DRC, and LVS

Verification in System Bench

Ansoft Nexxim + Designer


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